Logic realisation of a spatial domain image watermarking with single electron transistors – an innovative approach

Abhishek Basu, Arpita Ghosh and Anirban Mukherjee

International Journal of Critical Infrastructures, 2025, vol. 21, issue 4, 338-358

Abstract: Multimedia articles exchanged over the digital network are increasing day by day causing enhanced threats of losing authenticity or copyright of those contents. As a result, requirement for low power and high speed copyright protection system for multimedia objects is hovering. In this article, authors have projected one spatial domain-based image watermarking structure for multimedia copyright protection and its hardware level implementation based on field programmable gate array (FPGA). Moreover, single electron transistor (SET) implementation for the structure has also been presented. The technique uses least significant bit (LSB) plane-based information hiding and all the modules of embedding and extraction block are realised with SET. It has been observed that this scheme shows noteworthy imperceptibility along with robustness. The result of SET execution confirms significantly low power consumption.

Keywords: image watermarking; multimedia copyright protection; field programmable gate array; FPGA; single electron transistor; SET; least significant bit; LSB; low power. (search for similar items in EconPapers)
Date: 2025
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