Source and IR-level optimisations in the HercuLeS high-level synthesis tool

Nikolaos Kavvadias and Kostas Masselos

International Journal of Innovation and Regional Development, 2015, vol. 6, issue 3, 243-266

Abstract: HercuLeS is an extensible high-level synthesis environment for automatically mapping algorithms to hardware. It overcomes limitations of known work: insufficient representations, maintenance difficulties, necessity of code templates, lack of usage paradigms and vendor-dependence. Aspects that are highlighted include automatic IP integration and especially source- and intermediate-level optimising transformations. In this context, we present transformational patterns for loop and if-conversion optimisations. Further, we focus on constant multiplication and division by proposing a suitable scheme for their straightforward and decoupled utilisation in user applications. It is shown that loop optimisations provide benefits of up to 32% in cycle performance, while if-conversion delivers an average improvement of 6.5%. By applying arithmetic optimisations, a 3.3-5.9× speedup over sequential implementations is achieved. It is also shown that HercuLeS is highly competitive to state-of-the-art commercial tools.

Keywords: hardware; integrated circuits; field-programmable gate arrays; FPGAs; register transfer level; RTL; high-level synthesis; HLS; optimisation; algorithm mapping; transformational patterns; loop optimisation; if-conversion optimisation. (search for similar items in EconPapers)
Date: 2015
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