A functional unit network for rapid, low-power loop execution

Georgios Dimitriou and Athanasios Tziouvaras

International Journal of Innovation and Regional Development, 2015, vol. 6, issue 3, 267-284

Abstract: Computer architects have focused on advanced processor designs that achieve high performance through multiple cores and multiple threads, and at the same time keep power dissipation low. In this work, we propose a processor back end, specifically designed for rapid loop execution and low power dissipation. This back end consists of a network of functional unit nodes, in which instructions of the loop body are issued only once until loop completion. In this way, we exploit both instruction-level and data-flow parallelism. We attempt to decrease power consumption by turning off the front end and all unused functional units. Simulation results show that the proposed back end can accelerate Livermore loops by up to N/k, for a network of N units and loop body size of N instructions, and an issue rate of k instructions per cycle, when compared to scalar or superscalar RISC execution.

Keywords: processor architecture; processor back end; functional units; rapid loop execution; loop acceleration; dataflow parallelism; on-chip interconnects; low power dissipation; loop distribution; power consumption; simulation. (search for similar items in EconPapers)
Date: 2015
References: Add references at CitEc
Citations:

Downloads: (external link)
http://www.inderscience.com/link.php?id=71091 (text/html)
Access to full text is restricted to subscribers.

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:ids:ijirde:v:6:y:2015:i:3:p:267-284

Access Statistics for this article

More articles in International Journal of Innovation and Regional Development from Inderscience Enterprises Ltd
Bibliographic data for series maintained by Sarah Parker ().