Modelling and analysis of a multi-stage system involving batch processors with incompatible job families

John Benedict C. Tajan, Appa Iyer Sivakumar and Stanley B. Gershwin

International Journal of Operational Research, 2013, vol. 17, issue 4, 449-482

Abstract: Batch processors can concurrently process more than one job, and are commonly used in complex manufacturing systems such as wafer fabrication facilities (wafer fabs). Previous work has shown that there can be a significant reduction in cycle time when the control of the upstream serial processor is dependent on the batch processor. We wish to determine whether this is also true when the upstream processor is also a batch processor, with smaller capacity. We model a two-stage system with an upstream batch processor and a downstream batch processor under differing simple control policies as a continuous time-discrete state Markov chain. In doing so, we show that the concept of constraining the production of the upstream processor in accordance to the anticipated needs of the downstream batch processor can similarly reduce mean system cycle time when the upstream processor is a smaller batch processor. We also perform simulation experiments, using parameters close to those found in wafer fabs, and confirm that the strategy of prioritising the formation of larger batches for the downstream batch processor typically results in substantial cycle time reductions for the two-stage system.

Keywords: semiconductor manufacturing; heuristics; batch processors; cycle time reduction; modelling; multi-stage systems; incompatible job families; simulation; wafer fabrication. (search for similar items in EconPapers)
Date: 2013
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