User Authentication based on Dynamic Keystroke Recognition

Khaled Mohammed Fouad, Basma Mohammed Hassan and Mahmoud F. Hassan
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Khaled Mohammed Fouad: Department of Information Systems, Faculty of Computers and Informatics, Benha University, Benha, Egypt
Basma Mohammed Hassan: Department of Electrical Engineering Technology, Faculty of Engineering, Benha University, Benha, Egypt
Mahmoud F. Hassan: Department of Basic Sciences, Faculty of Engineering, Benha University, Benha, Egypt

International Journal of Ambient Computing and Intelligence (IJACI), 2016, vol. 7, issue 2, 1-32

Abstract: Biometric identification is a very good candidate technology, which can facilitate a trusted user authentication with minimum constraints on the security of the access point. However, most of the biometric identification techniques require special hardware, thus complicate the access point and make it costly. Keystroke recognition is a biometric identification technique which relies on the user behavior while typing on the keyboard. It is a more secure and does not need any additional hardware to the access point. This paper presents a developed behavioral biometric authentication method which enables to identify the user based on his Keystroke Static Authentication (KSA) and describes an authentication system that explains the ability of keystroke technique to authenticate the user based on his template profile saved in the database. Also, an algorithm based on dynamic keystroke analysis has been presented, synthesized, simulated and implemented on Field Programmable Gate Array (FPGA). The proposed algorithm is tested on 25 individuals, achieving a False Rejection Rate (FRR) about 4% and a False Acceptance Rate (FAR) about 0%. This performance is reached using the same sampling text for all the individuals. In this paper, two methods are used to implement the proposed approach: method one (H/W based Sorter) and method two (S/W based Sorter) are achieved execution time about 50.653 ns and 9.650 ns, respectively. Method two achieved a lower execution time; the time in which the proposed algorithm is executed on FPGA board, compared to some published results. As the second method achieved a small execution time and area utilization so it is the preferred method to be implemented on FPGA.

Date: 2016
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