Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor

Rajeev Sobti and Geetha Ganesan
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Rajeev Sobti: Lovely Professional University, Punjab, India
Geetha Ganesan: Lovely Professional University, Punjab, India

International Journal of Information Security and Privacy (IJISP), 2018, vol. 12, issue 1, 63-73

Abstract: SHA-3 was an open competition initiated by NIST to design new generation of hash functions. This competition was a necessity to overcome the challenges imposed by multiple attacks on MDx family of hash functions including SHA-0 and SHA-1. For this competition, NIST announced a reference platform which did not cover Embedded and Mobile machines. This paper compares the performance of SHA-3 final round candidate algorithms on ARM Cortex-M4 processor (embedded processor) and presents the results. Cycles per Byte is used as performance metric. Cortex-M4 based Stellaris® LM4F232 Evaluation Board (EK-LM4F232) from Texas Instruments is used for performance evaluation.

Date: 2018
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