Implementation of Improved Hash and Mapping Modified Low Power Parallel Bloom Filter Design

K. Saravanan and A. Senthilkumar
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K. Saravanan: Department of Electronics and Communication, Nehru Institute of Technology, Coimbatore, Tamil Nadu, India
A. Senthilkumar: Department of Electrical and Electronics, Dr. Mahalingam College of Engineering and Technology, Pollachi, Tamil Nadu, India

International Journal of Information Security and Privacy (IJISP), 2013, vol. 7, issue 4, 11-21

Abstract: In this article, the authors present an investigation on bloom filters and introduce a new improved variant, which uses a secure modified hash function and suggested improved mapping scheme with an efficient parallel architecture. This novel architecture provides efficient, relatively fast membership querying and compact information representation with negligible false positive. This is relatively a low power and secure design with very less false positive ratio when compared with the traditional bloom filters. The design has been evaluated and tested using Xilinx 65 nm Virtex-5 field-programmable gate array as the target technology. The performance matrices are false positive ratio, power, speed and compactness.

Date: 2013
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Persistent link: https://EconPapers.repec.org/RePEc:igg:jisp00:v:7:y:2013:i:4:p:11-21

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