Research on Cache Timing Attack Against RSA with Sliding Window Exponentiation Algorithm
Caisen Chen,
Yangxia Xiang,
Yuqin DengLiu and
Zeyun Zhou
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Caisen Chen: Ministry of Science Research, Academy of Armored Forces Engineering, Beijing, China
Yangxia Xiang: Department of Information Engineering, Academy of Armored Forces Engineering, Beijing, China
Yuqin DengLiu: Department of Information Engineering, Academy of Armored Forces Engineering, Beijing, China
Zeyun Zhou: Ministry of Science Research, Academy of Armored Forces Engineering, Beijing, China
International Journal of Interdisciplinary Telecommunications and Networking (IJITN), 2016, vol. 8, issue 2, 88-95
Abstract:
The vulnerabilities of the RSA cryptographic algorithm are analyzed, and it is not securely implemented. As the simultaneous multithreading could enable multiple execution threads to share the execution resources of a superscalar between the chipper process and the spy process, the shared access to memory caches provides an easily used high bandwidth covert channel between threads, allowing that a malicious thread can monitor the execution of another thread. This paper targets at RSA algorithm which is implemented with sliding window exponentiation algorithm via OpenSSL, the attacker can monitor the cryptographic thread by executing a spy thread, recording the timing characteristic during the RSA decryption when reading the Cache. The attacker can recover the original key via analyzing these timing measurements. Finally, the authors provide some countermeasures of how this attack could be mitigated or eliminated entirely.
Date: 2016
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Persistent link: https://EconPapers.repec.org/RePEc:igg:jitn00:v:8:y:2016:i:2:p:88-95
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