Formal Verification with ABV: A Superior Alternative to UVM for Complex Computing Chips

Kaushik Velapa Reddy

International Journal of Scientific Research in Computer Science, Engineering and Information Technology, 2024, vol. 10, issue 6, 90-98

Abstract: This article explores the evolution and effectiveness of formal verification enhanced with Assertion-Based Verification (ABV) as a superior alternative to traditional Universal Verification Methodology (UVM) in complex computing chip design. Through analysis of implementation data from major semiconductor companies, including Intel's Core i7 and IBM's POWER processors, the article demonstrates how formal methods achieve up to 100% coverage of critical modules compared to UVM's typical 80-85% coverage. The research presents quantitative evidence of formal verification's advantages, including a 25-30% reduction in verification cycles, a 40% increase in security vulnerability detection, and a 55% reduction in overall verification time through advanced techniques such as compositional verification and proof decomposition. The article also addresses scalability challenges and resource optimization strategies, providing a comprehensive framework for implementing formal verification in modern chip design workflows.

Keywords: Formal Verification; Assertion-Based Verification; Universal Verification Methodology; Scalability Optimization; Hardware Verification (search for similar items in EconPapers)
Date: 2024
Note: Article URL: https://ijsrcseit.com/home/article/view/CSEIT24106157
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Persistent link: https://EconPapers.repec.org/RePEc:jbh:ijsrcs:v10:y2024:i6:id:397

DOI: 10.32628/CSEIT24106157

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