An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations

Yin Wang, Hongwei Tang, Yufeng Xie, Xinyu Chen, Shunli Ma, Zhengzong Sun, Qingqing Sun, Lin Chen, Hao Zhu, Jing Wan, Zihan Xu, David Wei Zhang, Peng Zhou () and Wenzhong Bao ()
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Yin Wang: Fudan University
Hongwei Tang: Fudan University
Yufeng Xie: Fudan University
Xinyu Chen: Fudan University
Shunli Ma: Fudan University
Zhengzong Sun: Fudan University
Qingqing Sun: Fudan University
Lin Chen: Fudan University
Hao Zhu: Fudan University
Jing Wan: Fudan University
Zihan Xu: Shenzhen Sixcarbon Technology
David Wei Zhang: Fudan University
Peng Zhou: Fudan University
Wenzhong Bao: Fudan University

Nature Communications, 2021, vol. 12, issue 1, 1-8

Abstract: Abstract In-memory computing may enable multiply-accumulate (MAC) operations, which are the primary calculations used in artificial intelligence (AI). Performing MAC operations with high capacity in a small area with high energy efficiency remains a challenge. In this work, we propose a circuit architecture that integrates monolayer MoS2 transistors in a two-transistor–one-capacitor (2T-1C) configuration. In this structure, the memory portion is similar to a 1T-1C Dynamic Random Access Memory (DRAM) so that theoretically the cycling endurance and erase/write speed inherit the merits of DRAM. Besides, the ultralow leakage current of the MoS2 transistor enables the storage of multi-level voltages on the capacitor with a long retention time. The electrical characteristics of a single MoS2 transistor also allow analog computation by multiplying the drain voltage by the stored voltage on the capacitor. The sum-of-product is then obtained by converging the currents from multiple 2T-1C units. Based on our experiment results, a neural network is ex-situ trained for image recognition with 90.3% accuracy. In the future, such 2T-1C units can potentially be integrated into three-dimensional (3D) circuits with dense logic and memory layers for low power in-situ training of neural networks in hardware.

Date: 2021
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DOI: 10.1038/s41467-021-23719-3

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