Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning

Xinyu Chen, Yufeng Xie, Yaochen Sheng, Hongwei Tang, Zeming Wang, Yu Wang, Yin Wang, Fuyou Liao, Jingyi Ma, Xiaojiao Guo, Ling Tong, Hanqi Liu, Hao Liu, Tianxiang Wu, Jiaxin Cao, Sitong Bu, Hui Shen, Fuyu Bai, Daming Huang, Jianan Deng, Antoine Riaud, Zihan Xu, Chenjian Wu, Shiwei Xing, Ye Lu, Shunli Ma, Zhengzong Sun, Zhongyin Xue, Zengfeng Di, Xiao Gong, David Wei Zhang, Peng Zhou (), Jing Wan () and Wenzhong Bao ()
Additional contact information
Xinyu Chen: Fudan University
Yufeng Xie: Fudan University
Yaochen Sheng: Fudan University
Hongwei Tang: Fudan University
Zeming Wang: Fudan University
Yu Wang: Fudan University
Yin Wang: Fudan University
Fuyou Liao: Fudan University
Jingyi Ma: Fudan University
Xiaojiao Guo: Fudan University
Ling Tong: Fudan University
Hanqi Liu: Fudan University
Hao Liu: Fudan University
Tianxiang Wu: Fudan University
Jiaxin Cao: Fudan University
Sitong Bu: Fudan University
Hui Shen: Fudan University
Fuyu Bai: Fudan University
Daming Huang: Fudan University
Jianan Deng: Fudan University
Antoine Riaud: Fudan University
Zihan Xu: Shenzhen Six Carbon Technology
Chenjian Wu: Soochow University
Shiwei Xing: Soochow University
Ye Lu: Fudan University
Shunli Ma: Fudan University
Zhengzong Sun: Fudan University
Zhongyin Xue: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
Zengfeng Di: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
Xiao Gong: National University of Singapore
David Wei Zhang: Fudan University
Peng Zhou: Fudan University
Jing Wan: Fudan University
Wenzhong Bao: Fudan University

Nature Communications, 2021, vol. 12, issue 1, 1-8

Abstract: Abstract Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials.

Date: 2021
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DOI: 10.1038/s41467-021-26230-x

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