An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions

Senfeng Zeng, Chunsen Liu (), Xiaohe Huang, Zhaowu Tang, Liwei Liu and Peng Zhou ()
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Senfeng Zeng: State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University
Chunsen Liu: State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University
Xiaohe Huang: State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University
Zhaowu Tang: State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University
Liwei Liu: State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University
Peng Zhou: State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University

Nature Communications, 2022, vol. 13, issue 1, 1-9

Abstract: Abstract With the rapid development of artificial intelligence, parallel image processing is becoming an increasingly important ability of computing hardware. To meet the requirements of various image processing tasks, the basic pixel processing unit contains multiple functional logic gates and a multiplexer, which leads to notable circuit redundancy. The pixel processing unit retains a large optimizing space to solve the area redundancy issues in parallel computing. Here, we demonstrate a pixel processing unit based on a single WSe2 transistor that has multiple logic functions (AND and XNOR) that are electrically switchable. We further integrate these pixel processing units into a low transistor-consumption image processing array, where both image intersection and image comparison tasks can be performed. Owing to the same image processing power, the consumption of transistors in our image processing unit is less than 16% of traditional circuits.

Date: 2022
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DOI: 10.1038/s41467-021-27644-3

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