Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors

Junhwan Choi, Changhyeon Lee, Chungryeol Lee, Hongkeun Park, Seung Min Lee, Chang-Hyun Kim, Hocheon Yoo () and Sung Gap Im ()
Additional contact information
Junhwan Choi: Department of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu
Changhyeon Lee: Department of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu
Chungryeol Lee: Department of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu
Hongkeun Park: Department of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu
Seung Min Lee: Department of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu
Chang-Hyun Kim: Department of Electronic Engineering Gachon University 1342 Seongnam-daero, Sujeong-gu
Hocheon Yoo: Department of Electronic Engineering Gachon University 1342 Seongnam-daero, Sujeong-gu
Sung Gap Im: Department of Chemical and Biomolecular Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu

Nature Communications, 2022, vol. 13, issue 1, 1-10

Abstract: Abstract Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to control the channel conductance systematically, thus realizing the stabilized T-inverter operation. The 3-dimensional (3D) T-inverter is fabricated in a vertically stacked form based on all-dry processes, which enables the high-density integration with high device uniformity. In the flash memory, ultrathin polymer dielectrics are utilized to reduce the programming/erasing voltage as well as operating voltage. With the optimum programming state, the 3D T-inverter fulfills all the important requirements such as full-swing operation, optimum intermediate logic value (~VDD/2), high DC gain exceeding 20 V/V as well as low-voltage operation (

Date: 2022
References: View references in EconPapers View complete reference list from CitEc
Citations:

Downloads: (external link)
https://www.nature.com/articles/s41467-022-29756-w Abstract (text/html)

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:nat:natcom:v:13:y:2022:i:1:d:10.1038_s41467-022-29756-w

Ordering information: This journal article can be ordered from
https://www.nature.com/ncomms/

DOI: 10.1038/s41467-022-29756-w

Access Statistics for this article

Nature Communications is currently edited by Nathalie Le Bot, Enda Bergin and Fiona Gillespie

More articles in Nature Communications from Nature
Bibliographic data for series maintained by Sonal Shukla () and Springer Nature Abstracting and Indexing ().