Hardware functional obfuscation with ferroelectric active interconnects

Tongguang Yu, Yixin Xu, Shan Deng, Zijian Zhao, Nicolas Jao, You Sung Kim, Stefan Duenkel, Sven Beyer, Kai Ni (), Sumitha George () and Vijaykrishnan Narayanan
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Tongguang Yu: Pennsylvania State University
Yixin Xu: Pennsylvania State University
Shan Deng: Rochester Institute of Technology
Zijian Zhao: Rochester Institute of Technology
Nicolas Jao: Pennsylvania State University
You Sung Kim: GlobalFoundries Fab1 LLC & Co. KG
Stefan Duenkel: GlobalFoundries Fab1 LLC & Co. KG
Sven Beyer: GlobalFoundries Fab1 LLC & Co. KG
Kai Ni: Rochester Institute of Technology
Sumitha George: North Dakota State University
Vijaykrishnan Narayanan: Pennsylvania State University

Nature Communications, 2022, vol. 13, issue 1, 1-11

Abstract: Abstract Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.

Date: 2022
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DOI: 10.1038/s41467-022-29795-3

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