Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory

Maosong Xie, Yueyang Jia, Chen Nie, Zuheng Liu, Alvin Tang, Shiquan Fan, Xiaoyao Liang, Li Jiang, Zhezhi He () and Rui Yang ()
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Maosong Xie: University of Michigan—Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University
Yueyang Jia: University of Michigan—Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University
Chen Nie: Shanghai Jiao Tong University
Zuheng Liu: University of Michigan—Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University
Alvin Tang: Stanford University
Shiquan Fan: Xi’an Jiaotong University
Xiaoyao Liang: Shanghai Jiao Tong University
Li Jiang: Shanghai Jiao Tong University
Zhezhi He: Shanghai Jiao Tong University
Rui Yang: University of Michigan—Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University

Nature Communications, 2023, vol. 14, issue 1, 1-11

Abstract: Abstract Emerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS2) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems.

Date: 2023
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DOI: 10.1038/s41467-023-41736-2

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