A near-threshold memristive computing-in-memory engine for edge intelligence

Linfang Wang, Weizeng Li, Zhidao Zhou, Junjie An, Wang Ye, Zhi Li, Hanghang Gao, Hongyang Hu, Jing Liu, Xiaoming Chen, Ling Li, Qi Liu, Mingoo Seok, Chunmeng Dou () and Ming Liu
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Linfang Wang: Institute of Microelectronics of the Chinese Academy of Sciences
Weizeng Li: Institute of Microelectronics of the Chinese Academy of Sciences
Zhidao Zhou: Institute of Microelectronics of the Chinese Academy of Sciences
Junjie An: Institute of Microelectronics of the Chinese Academy of Sciences
Wang Ye: Institute of Microelectronics of the Chinese Academy of Sciences
Zhi Li: Institute of Microelectronics of the Chinese Academy of Sciences
Hanghang Gao: Institute of Microelectronics of the Chinese Academy of Sciences
Hongyang Hu: Institute of Microelectronics of the Chinese Academy of Sciences
Jing Liu: Institute of Microelectronics of the Chinese Academy of Sciences
Xiaoming Chen: Institute of Computing Technology of the Chinese Academy of Sciences
Ling Li: Institute of Software of the Chinese Academy of Sciences
Qi Liu: Institute of Microelectronics of the Chinese Academy of Sciences
Mingoo Seok: Columbia University
Chunmeng Dou: Institute of Microelectronics of the Chinese Academy of Sciences
Ming Liu: Institute of Microelectronics of the Chinese Academy of Sciences

Nature Communications, 2025, vol. 16, issue 1, 1-10

Abstract: Abstract Memristive computing-in-memory and near-threshold computing are two unconventional computing paradigms that can potentially enhance the energy efficiency and real-time performance of edge devices. However, their scalability faces challenges, primarily due to process variation. Here, we report a 1-Mb, 16-macro near-threshold memristive computing-in-memory engine. The two-transistor-one-resistor cells provide strong cell current modulation capability with more than 120-times amplified resistance ratio. To mitigate variation issues, we compensate for transistor mismatches by leveraging the intrinsic variations in memristors. Additionally, we propose a charge stacking technique between multiple analog-to-digital converters to perform analog weight-and-combine operations with small energy and area overhead. Moreover, we introduce an inter-macro hybrid control scheme to reduce the task-level inference power. The fabricated chip can perform highly parallel analog computing over 256 input channels with a 2.4% relative standard deviation. It achieves a throughput up to 10.49 tera-operations per second and an energy efficiency up to 88.51 tera-operations per second per watt.

Date: 2025
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DOI: 10.1038/s41467-025-61025-4

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