11-bit two-dimensional floating-gate memories
Yanrong Wang,
Yuchen Cai,
Feng Wang (),
Tao Yan,
Shuhui Li,
Mingyang Cao,
Ruohao Hong,
Baoxing Zhai,
Kai Xu,
Xueying Zhan,
Jun He and
Zhenxing Wang ()
Additional contact information
Yanrong Wang: Henan Academy of Sciences
Yuchen Cai: National Center for Nanoscience and Technology
Feng Wang: National Center for Nanoscience and Technology
Tao Yan: University of Chinese Academy of Sciences
Shuhui Li: National Center for Nanoscience and Technology
Mingyang Cao: Henan Academy of Sciences
Ruohao Hong: Henan Academy of Sciences
Baoxing Zhai: Henan Academy of Sciences
Kai Xu: Zhejiang University
Xueying Zhan: National Center for Nanoscience and Technology
Jun He: Henan Academy of Sciences
Zhenxing Wang: National Center for Nanoscience and Technology
Nature Communications, 2025, vol. 16, issue 1, 1-9
Abstract:
Abstract Floating-gate memories (FGMs) show great promise for neuromorphic computing in efficient data-centric applications. However, their limited single-device state capacity remains insufficient for highly integrated precision computing. Here, we demonstrate 11-bit two-dimensional (2D) MoS2 FGMs by contacting the 2D channels with bismuth electrodes, enabling 100 μA on-state current with 108 on/off ratio and reducing the current noise by 3 times (approaching the equipment limits) due to the Schottky barrier-free interfaces. Moreover, we employed a dual-pulse state editing scheme enhancing the stability of our FGMs. The devices show as high as 2,249 distinct conductance levels (>11-bit) while maintaining 230 ns operation speed, >104 s retention, and >105 cycle endurance. Furthermore, the gate-injection operation prevents the influence from generated defects during cycling, maintaining low noise even after 105 cycles and at 85 °C. Theoretical analysis reveals interfacial defects as the primary state-number limitation, suggesting 17-bit capacity is achievable through further trap density reduction. This work establishes 2D FGMs as promising candidates for high-bit-density, low-power neuromorphic hardware.
Date: 2025
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DOI: 10.1038/s41467-025-64333-x
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