CMOS-based carbon nanotube pass-transistor logic integrated circuits
Li Ding,
Zhiyong Zhang,
Shibo Liang,
Tian Pei,
Sheng Wang,
Yan Li,
Weiwei Zhou,
Jie Liu and
Lian-Mao Peng ()
Additional contact information
Li Ding: Key Laboratory for the Physics and Chemistry of Nanodevices, Peking University
Zhiyong Zhang: Key Laboratory for the Physics and Chemistry of Nanodevices, Peking University
Shibo Liang: Key Laboratory for the Physics and Chemistry of Nanodevices, Peking University
Tian Pei: Key Laboratory for the Physics and Chemistry of Nanodevices, Peking University
Sheng Wang: Key Laboratory for the Physics and Chemistry of Nanodevices, Peking University
Yan Li: Key Laboratory for the Physics and Chemistry of Nanodevices, and College of Chemistry and Molecular Engineering, Peking University
Weiwei Zhou: Duke University
Jie Liu: Duke University
Lian-Mao Peng: Key Laboratory for the Physics and Chemistry of Nanodevices, Peking University
Nature Communications, 2012, vol. 3, issue 1, 1-7
Abstract:
Abstract Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.
Date: 2012
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Persistent link: https://EconPapers.repec.org/RePEc:nat:natcom:v:3:y:2012:i:1:d:10.1038_ncomms1682
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DOI: 10.1038/ncomms1682
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