Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

R.A. Minamisawa (), M.J. Süess, R. Spolenak, J. Faist, C. David, J. Gobrecht, K.K. Bourdelle and H. Sigg ()
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R.A. Minamisawa: Laboratory for Micro- and Nanotechnology, Paul Scherrer Institut
M.J. Süess: Electron Microscopy, ETH Zürich
R. Spolenak: Laboratory for Nanometallurgy, ETH Zürich
J. Faist: Institute for Quantum Electronics, ETH Zürich
C. David: Laboratory for Micro- and Nanotechnology, Paul Scherrer Institut
J. Gobrecht: Laboratory for Micro- and Nanotechnology, Paul Scherrer Institut
K.K. Bourdelle: SOITEC, Parc Technologique des Fontaines
H. Sigg: Laboratory for Micro- and Nanotechnology, Paul Scherrer Institut

Nature Communications, 2012, vol. 3, issue 1, 1-6

Abstract: Abstract Strained Si nanowires are among the most promising transistor structures for implementation in very large-scale integration due to of their superior electrostatic control and enhanced transport properties. Realizing even higher strain levels within such nanowires are thus one of the current challenges in microelectronics. Here we achieve 4.5% of elastic strain (7.6 GPa uniaxial tensile stress) in 30 nm wide Si nanowires, which considerably exceeds the limit that can be obtained using SiGe-based virtual substrates. Our approach is based on strain accumulation mechanisms in suspended dumbbell-shaped bridges patterned on strained Si-on-insulator, and is compatible with complementary metal oxide semiconductor fabrication. Potentially, this method can be applied to any tensile prestrained layer, provided the layer can be released from the substrate, enabling the fabrication of a variety of strained semiconductors with unique properties for applications in nanoelectronics, photonics and photovoltaics. This method also opens up opportunities for research on strained materials.

Date: 2012
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DOI: 10.1038/ncomms2102

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