Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

Labonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Alauddin Mohammad Ali and Mohammad Marufuzzaman

PLOS ONE, 2014, vol. 9, issue 10, 1-12

Abstract: The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.

Date: 2014
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Persistent link: https://EconPapers.repec.org/RePEc:plo:pone00:0108634

DOI: 10.1371/journal.pone.0108634

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