OPTIMIZING LARGE COMBINATIONAL NETWORKS FOR K-LUT BASED FPGA MAPPING
Ion I. Bucur,
Ioana Făgărăşan,
Cornel Popescu,
George Culea and
Alexandru E. Şuşu
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Ion I. Bucur: University Politehnica of Bucharest
Ioana Făgărăşan: University Politehnica of Bucharest
Cornel Popescu: University Politehnica of Bucharest
George Culea: University of Bacǎu, Faculty of Electrical Engineering
Alexandru E. Şuşu: Swiss Federal Institute of Technology Lausanne
Journal of Information Systems & Operations Management, 2008, vol. 2, issue 1, 154-165
Abstract:
Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packages
Keywords: two-way partitioning; multi-way partitioning; recursive partitioning; flat partitioning; critical path; cutting cones; bottom-up clusters; top-down min-cut (search for similar items in EconPapers)
Date: 2008
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Persistent link: https://EconPapers.repec.org/RePEc:rau:jisomg:v:2:y:2008:i:1:p:154-165
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