OPTIMAL AREA AND PERFORMANCE MAPPING OF K-LUT BASED FPGAS

Ion I. Bucur, Cornel Popescu, George Culea and Alexandru E. Şuşu
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Ion I. Bucur: University Politehnica of Bucharest
Cornel Popescu: University Politehnica of Bucharest
George Culea: University of Bacǎu
Alexandru E. Şuşu: Swiss Federal Institute of Technology Lausanne

Journal of Information Systems & Operations Management, 2008, vol. 2, issue 2, 375-390

Abstract: FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map, both for area and performance, combinational networks using k-LUT based FPGAs.

Keywords: k-LUT based FPGAs; combinational circuits; performance-driven mapping. (search for similar items in EconPapers)
Date: 2008
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