ESTIMATING SPURIOUS POWER WHILE MAPPING K-LUT-BASED FPGA CIRCUITS

Ion Bucur (), Nicolae Cupcea (), Adrian Surpateanu () and Cornel Popescu ()
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Ion Bucur: University Politehnica of Bucharest
Nicolae Cupcea: University Politehnica of Bucharest
Adrian Surpateanu: University Politehnica of Bucharest
Cornel Popescu: University Politehnica of Bucharest

Journal of Information Systems & Operations Management, 2009, vol. 3, issue 2, 388-397

Abstract: In this paper is presented a new approach for decreasing the spurious power consumption in K-LUT based FPGA implemented circuits. The approach is based on selective collapsing nodes in a direct acyclic graph (DAG) representing combinational or synchronous sequential circuits. It was used the simulation-based approach that estimates, using Monte Carlo experiment, the spurious switching activity of each net in the circuit. Traversing circuits in topological order, step by step best K-feasible cone are computed at the output of each node. Preserving the best depth of the circuits the mapping stage is done searching to minimize spurious switching power.

Keywords: spurious switching power; K-feasible cones; optimum depth; optimal area and power (search for similar items in EconPapers)
Date: 2009
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