Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance

Keerthi Dorai Swamy Reddy (), Eduardo Pérez (), Andrea Baroni (), Mamathamba Kalishettyhalli Mahadevaiah (), Steffen Marschmeyer (), Mirko Fraschke (), Marco Lisker (), Christian Wenger () and Andreas Mai ()
Additional contact information
Keerthi Dorai Swamy Reddy: IHP GmbH-Leibniz Institute for High Performance Microelectronics
Eduardo Pérez: IHP GmbH-Leibniz Institute for High Performance Microelectronics
Andrea Baroni: IHP GmbH-Leibniz Institute for High Performance Microelectronics
Mamathamba Kalishettyhalli Mahadevaiah: IHP GmbH-Leibniz Institute for High Performance Microelectronics
Steffen Marschmeyer: IHP GmbH-Leibniz Institute for High Performance Microelectronics
Mirko Fraschke: IHP GmbH-Leibniz Institute for High Performance Microelectronics
Marco Lisker: IHP GmbH-Leibniz Institute for High Performance Microelectronics
Christian Wenger: IHP GmbH-Leibniz Institute for High Performance Microelectronics
Andreas Mai: IHP GmbH-Leibniz Institute for High Performance Microelectronics

The European Physical Journal B: Condensed Matter and Complex Systems, 2024, vol. 97, issue 11, 1-9

Abstract: Abstract Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of $$\hbox {HfO}_2$$ HfO 2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm $$\hbox {HfO}_2$$ HfO 2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. Graphical abstract

Date: 2024
References: View references in EconPapers View complete reference list from CitEc
Citations:

Downloads: (external link)
http://link.springer.com/10.1140/epjb/s10051-024-00821-1 Abstract (text/html)
Access to the full text of the articles in this series is restricted.

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:spr:eurphb:v:97:y:2024:i:11:d:10.1140_epjb_s10051-024-00821-1

Ordering information: This journal article can be ordered from
http://www.springer.com/economics/journal/10051

DOI: 10.1140/epjb/s10051-024-00821-1

Access Statistics for this article

The European Physical Journal B: Condensed Matter and Complex Systems is currently edited by P. Hänggi and Angel Rubio

More articles in The European Physical Journal B: Condensed Matter and Complex Systems from Springer, EDP Sciences
Bibliographic data for series maintained by Sonal Shukla () and Springer Nature Abstracting and Indexing ().