Analysis of cache behaviour and software optimizations for faster on-chip network simulations

B. M. Prabhu Prasad (), Khyamling Parane () and Basavaraj Talawar ()
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B. M. Prabhu Prasad: National Institute of Technology Karnataka, Surathkal
Khyamling Parane: National Institute of Technology Karnataka, Surathkal
Basavaraj Talawar: National Institute of Technology Karnataka, Surathkal

International Journal of System Assurance Engineering and Management, 2019, vol. 10, issue 4, No 20, 696-712

Abstract: Abstract Fast simulations are critical in reducing time to market in chip multiprocessors and system-on-chips. Several simulators have been used to evaluate the performance and power consumed by network-on-chips (NoCs). To speedup the simulations, it is necessary to investigate and optimize the hotspots in the simulator source code. Among several simulators available, Booksim2.0 has been chosen for the experimentation as it is being extensively used in the NoC community. In this paper, the cache and memory system behavior of Booksim2.0 have been analyzed to accurately monitor input dependent performance bottlenecks. The measurements show that cache and memory usage patterns vary widely based on the input parameters given to Booksim2.0. Based on these measurements, the cache configuration having the least misses has been identified. To further reduce the cache misses, software optimization techniques such as removal of unused functions, loop interchanging and replacing post-increment operator with pre-increment operator for non-primitive data types have been employed. The cache misses were reduced by 18.52%, 5.34% and 3.91% by employing above technology respectively. Thread parallelization and vectorization have been employed to improve the overall performance of Booksim2.0. The OpenMP programming model and SIMD are used for parallelizing and vectorizing the more time-consuming portions of Booksim2.0. Speedups of 2.93× and 3.97× were observed for the Mesh topology with $$30\times 30$$ 30 × 30 network size by employing thread parallelization and vectorization respectively.

Keywords: Cache behaviour; Hotspot analysis; Network-on-chip; Parallelization; Performance profiling (search for similar items in EconPapers)
Date: 2019
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DOI: 10.1007/s13198-019-00799-5

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