Design and implementation of a new inverter topology with reduced THD and part count

Mudadla Dhananjaya, Swapnajit Pattnaik and Devendra Potnuru ()
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Mudadla Dhananjaya: ANITS
Swapnajit Pattnaik: National Institute of Technology
Devendra Potnuru: GVP College of Engineering for Women

International Journal of System Assurance Engineering and Management, 2022, vol. 13, issue 3, No 29, 1410-1418

Abstract: Abstract The quality of power generation from various energy sources is essential for industrial and household applications. To achieve the quality of power by reducing the Total Harmonic Distortion (THD) through multilevel inverters (MLIs) is an attractive solution. MLIs have drawn tremendous performance as compared to the classical two-level inverter for reducing the %THD and lower electromagnetic interference. However, MLIs having more device count and intricacy of the circuitry and reducing the THD further might affect the cost, size, and complexity of the circuit. In this paper, a new inverter topology is proposed to have a low level of THD and reduced part count. The proposed topology consists of a combination of the synchronous buck converter and cascaded with an H-bridge. This approach reduces the requirement of the number of isolated dc voltage sources, switches, and other components in addition to low %THD. More specifically, the proposed inverter does not need dc voltage sources of different values, minimizes the cost and size of the system as compared with the conventional and hybrid topologies. The effectiveness of the proposed converter is validated using the results of both simulations and experiments on the laboratory prototype of the 150 W converter.

Keywords: Inverter; Power quality; Total Harmonic Distortion (THD); Multilevel inverter (search for similar items in EconPapers)
Date: 2022
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DOI: 10.1007/s13198-021-01486-0

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