Low power multiplier based long short-term memory hardware architecture for smart grid energy management

Senthil Perumal () and Sandanalakshmi Rajendiran ()
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Senthil Perumal: Pondicherry Engineering College
Sandanalakshmi Rajendiran: Pondicherry Engineering College

International Journal of System Assurance Engineering and Management, 2022, vol. 13, issue 5, No 30, 2539 pages

Abstract: Abstract RNN (Recurrent Neural Network) based data analytics method has evolved as a best-integrated method for Energy management in Smart Grid. Long Short-Term Memory (LSTM) architecture mostly used in RNN, ensures better RMSE (Root Mean Square Error) values for Demand Management. Convolution methods in LSTM increases the complexity, low power multiplier based accelerator provides easier implementation of LSTM cells. ASIC (Application Specific Integrated Circuit) design for LSTM network architecture with low power multipliers based accelerators is proposed in this work. In ASIC, Look-Up Table (LUT) based concatenation cell ensures a single-cell low power consumption. The ratio of the leakage power to that of the dynamic power and the total power are 4.3% and 4.1%, respectively which is very less than the allowable limit. Also, it is shown that the proposed architecture reduces the LUT size over 50%, when compared with the existing architecture using Static Random Access Memory cell. The proposed architecture works for different precisions of RNN and can also lead to better System on Chip architectures for Deep RNN networks. On comparing the proposed low power multiplier based LSTM architecture with existing FPGA and ASIC based architectures, substantially low power consumption is reported without a significant loss in prediction accuracy.

Keywords: Long short-term memory; ASIC; Hardware acceleration; Recurrent neural network; Multipliers (search for similar items in EconPapers)
Date: 2022
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DOI: 10.1007/s13198-022-01662-w

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