High performance fir filter based on vedic mathematics

N. Mohana Priya (), C. Bennila Thangammal (), R. Seshasayanan () and Sheryl Radley ()
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N. Mohana Priya: Meenakshi College of Engineering
C. Bennila Thangammal: R.M.D. Engineering College
R. Seshasayanan: Meenakshi College of Engineering
Sheryl Radley: Meenakshi College of Engineering

International Journal of System Assurance Engineering and Management, 2023, vol. 14, issue 3, No 2, 829-835

Abstract: Abstract The FIR digital filter has linear phase, reduced finite precision errors, stability, and productive execution and it is used in Digital Signal Processing (DSP). Signal data processing applications require both signed and unsigned multiplications. Despite its high cost, signed Multiplications are used in a wide number of DSP applications. This paper propose signed vedic multiplier having High speed and low power for finite impulse response. High performance and low power is achieved by parallel operations and adopting Urdhva Triyakbhyam sutra (vertically and crosswise multiplication) in vedic multiplier. The proposed vedic multiplier architecture is implemented and compared with existing conventional radix-4 Booth multiplier.it is observed from the result that the proposed technique results in a 15% increase in speed and 52% reduction in power consumption.

Keywords: Digital signal processing; FIR filter; Urdhva Triyakbhyam sutra etc (search for similar items in EconPapers)
Date: 2023
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DOI: 10.1007/s13198-023-01899-z

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