Architectural analysis of 1-D to 2-D array conversion of priority encoder

Alok Kumar Mishra (), Shail Anand (), Nishant Singh (), Vaithiyanathan Dhandapani () and Baljit Kaur ()
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Alok Kumar Mishra: National Institute of Technology Delhi
Shail Anand: National Institute of Technology Delhi
Nishant Singh: National Institute of Technology Delhi
Vaithiyanathan Dhandapani: National Institute of Technology Delhi
Baljit Kaur: National Institute of Technology Delhi

International Journal of System Assurance Engineering and Management, 2023, vol. 14, issue 5, No 11, 1726-1737

Abstract: Abstract In this paper, a high-performance priority encoder of the 2-dimensional array is investigated and modified. This work involves 64-bit priority encoder design and verification using Verilog and cadence virtuoso. For the Verilog code, Vivado has been used for the Artix-7 FPGA board. For Cadence virtuoso, GPDK 180 nm CMOS technology has been used. By using a reduced 2-D priority encoder, 1000 transistors have been saved. Due to this, the delay of the whole 64-bit priority encoder is reduced by 62.17% as compared to PE64 and 61.68% as compared to modified PE64.

Keywords: High performance; Priority encoder; Artix-7; FPGA; Multiplexer (search for similar items in EconPapers)
Date: 2023
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DOI: 10.1007/s13198-023-01977-2

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