State of the art design of adder modules: performance validation of GDI methodology for energy harvesting applications

Puli Raju (), Vallabhuni Vijay (), P. Ashok Babu () and P. Sridhar ()
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Puli Raju: Institute of Aeronautical Engineering
Vallabhuni Vijay: Institute of Aeronautical Engineering
P. Ashok Babu: Institute of Aeronautical Engineering
P. Sridhar: Institute of Aeronautical Engineering

International Journal of System Assurance Engineering and Management, 2023, vol. 14, issue 6, No 12, 2176-2186

Abstract: Abstract Based on Gate Diffusion Input and Conventional Complementary Metal-Oxide Semiconductor logic, this study offers a full-swing high-speed hybrid Full Adder cell. The design was evaluated and compared to standard ten full adder designs for their key significance in real-time applications. The implementation uses the Cadence tool in the 18 nm FinFET module. The small size of MOSFETs (less than 28 nm nanometers) has caused specific operational issues in recent years, such as enhanced gate-oxide leakage, amplified junction leakage, strong sub-threshold conduction, and lowered output resistance. To solve the issues described above, FinFET offers the benefits of an increased operating speed, lower power consumption, and decreased static leakage current, which is utilized to realize most applications by replacing MOSFET. Considering the attractive characteristics of FinFETs, ten standard full adder cells have been designed and tested using FinFETs. The proposed design shows a significant improvement regarding speed and power delay products. The limitations of the proposed models are validated by increasing the adder cells to the maximum number of 64 bits.

Keywords: CMOS logic styles; EDP; FinFET; Gate diffusion input (GDI); Layout; PDP (search for similar items in EconPapers)
Date: 2023
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Citations: View citations in EconPapers (2)

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DOI: 10.1007/s13198-023-02047-3

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