Performance analysis of 1D-to-2D array conversion for priority encoders in post-layout design

Dhandapani Vaithiyanathan (), Abhishek Behera (), Alok Kumar Mishra () and Preeti Verma ()
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Dhandapani Vaithiyanathan: National Institute of Technology Delhi
Abhishek Behera: National Institute of Technology Delhi
Alok Kumar Mishra: National Institute of Technology Delhi
Preeti Verma: National Institute of Technology Delhi

International Journal of System Assurance Engineering and Management, 2025, vol. 16, issue 10, No 14, 3430-3439

Abstract: Abstract This paper presents post-layout analysis of a modified 64-bit Priority Encoder (PE) design optimized for speed and efficiency. Our previous research implemented a scalable 1D-to-2D array conversion technique for PE implementation, demonstrating its effectiveness in 4-bit, 16-bit, and 64-bit designs. Here, we extend this approach by analyzing the post-layout performance of a 1V 64-bit PE fabricated in an 180 nm CMOS process. Compared to a reference design, our post-layout simulations reveal a significant 47.37% improvement in operating frequency. This remarkable enhancement highlights the robustness and efficiency of our proposed PE architecture, making it particularly suitable for high-speed data processing applications.

Keywords: Multiplexer; Priority Encoder; Transmission gate; CMOS; VLSI (search for similar items in EconPapers)
Date: 2025
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DOI: 10.1007/s13198-025-02868-4

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