Advanced arithmetic circuits realization using next generation logic gates

Sreevani Menda (), Sivaji Satrasupalli (), Rajeev Ratna Vallabhuni () and S. China Venkateswarlu ()
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Sreevani Menda: Institute of Aeronautical Engineering
Sivaji Satrasupalli: SRM Institute of Science and Technology
Rajeev Ratna Vallabhuni: Lakeview Loan Servicing, LLC
S. China Venkateswarlu: Institute of Aeronautical Engineering

International Journal of System Assurance Engineering and Management, 2025, vol. 16, issue 6, No 6, 2078-2088

Abstract: Abstract The design of ternary Logic gates–Ternary NAND, Ternary NOR and Standard Ternary Inverter based on the 18 nm FinFET technology is proposed. The Ternary logic systems replaced Existing Binary logic systems with their good operating speed, energy efficiency, information density and reduced circuits like chip area and interconnections. Instead of using large Resistors, the proposed model consists of 18 nm FinFETs, reducing the number of resistors used. The proposed ternary logic gates are then used to carry the arithmetic operations that are basic and implement various complex functions. These ternary logic gates show the significant advantages of chip area, energy and power consumptions, denser fabrication and component count. The ternary half- adder and ternary half-subtractor circuits are then implemented by utilizing the proposed gates and then verified through the simulations. The results are then compared with the existing designs of MOSFET based Ternary logic gates. The parameters like power consumption are compared with the current MOSFET models, and then the proposed models are simulated. For simulations, Cadence Virtuoso tool and MATLAB are used to verify the authenticity of proposed designs.

Keywords: Ternary Logic Systems; Ternary half-adder; Ternary half-subtractor; Multiple Valued Logic (search for similar items in EconPapers)
Date: 2025
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DOI: 10.1007/s13198-025-02800-w

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