Approximation scheme for restricted discrete gate sizing targeting delay minimization

Chen Liao () and Shiyan Hu ()
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Chen Liao: Michigan Technological University
Shiyan Hu: Michigan Technological University

Journal of Combinatorial Optimization, 2011, vol. 21, issue 4, No 7, 497-510

Abstract: Abstract Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such that the delay of a combinational circuit is minimized while the cost constraint is satisfied. It is one of the most studied problems in VLSI computer-aided design. Despite this, all of the existing techniques are heuristics with no performance guarantee. This limits the understanding of the discrete gate sizing problem in theory. This paper designs the first fully polynomial time approximation scheme (FPTAS) for the delay driven discrete gate sizing problem. The proposed approximation scheme involves a level based dynamic programming algorithm which handles the specific structures of a discrete gate sizing problem and adopts an efficient oracle query procedure. It can approximate the optimal gate sizing solution within a factor of (1+ε) in O(n 1+c m 3c /ε c ) time for 0

Keywords: Combinatorial optimization; VLSI design; Delay optimization; Discrete gate sizing; Fully polynomial time approximation scheme (search for similar items in EconPapers)
Date: 2011
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DOI: 10.1007/s10878-009-9267-0

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