Optimal wafer cutting in shuttle layout problems

Lasse Nisted (), David Pisinger () and Avri Altman ()
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Lasse Nisted: University of Copenhagen
David Pisinger: Technical University of Denmark
Avri Altman: Intel

Journal of Combinatorial Optimization, 2011, vol. 22, issue 2, No 6, 202-216

Abstract: Abstract A major cost in semiconductor manufacturing is the generation of photo masks which are used to produce the dies. When producing smaller series of chips it can be advantageous to build a shuttle mask (or multi-project wafer) to share the startup costs by placing different dies on the same mask. The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible dies can be cut from a given wafer, and each cutting plan must respect various constraints on where the cuts may be placed. We present an exact algorithm for solving the minimum cutting plan problem, given a floorplan of the dies. The algorithm is based on delayed column generation, where the pricing problem becomes a maximum vertex-weighted clique problem in which each clique consists of cutting compatible dies. The resulting branch-and-price algorithm is able to solve realistic cutting problems to optimality in a couple of seconds.

Keywords: Semiconductor layout problem; Cutting problem; Column generation; Vertex-weighted clique problem (search for similar items in EconPapers)
Date: 2011
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DOI: 10.1007/s10878-009-9284-z

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