Race to idle or not: balancing the memory sleep time with DVS for energy minimization

Chenchen Fu (), Vincent Chau (), Minming Li () and Chun Jason Xue ()
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Chenchen Fu: City University of Hong Kong
Vincent Chau: City University of Hong Kong
Minming Li: City University of Hong Kong
Chun Jason Xue: City University of Hong Kong

Journal of Combinatorial Optimization, 2018, vol. 35, issue 3, No 12, 860-894

Abstract: Abstract Reducing energy consumption is a critical problem in most of the computing systems today. Among all the computing system components, processor and memory are two significant energy consumers. Dynamic voltage scaling is typically applied to reduce processor energy while sleep mode is usually injected to trim memory’s leakage energy. However, in the memory architecture with multiple cores sharing memory, in order to optimize the system-wide energy, these two classic techniques are difficult to be directly combined due to the complicated interactions. In this work, we explore the coordination of the multiple cores and the memory, and present systematic analysis for minimizing the system-wide energy based on different system models and task models. For tasks with common release time, optimal schemes are presented for the systems both with and without considering the static power of the cores. For agreeable deadline tasks, different dynamic programming-based optimal solutions are proposed for negligible and non-negligible static power of cores. For the general task model, this paper proposes a heuristic online algorithm. Furthermore, the scheme is extended to handle the problem when the transition overhead between the active and sleep modes is considered. The optimality of the proposed schemes for common release time and agreeable deadline tasks are proved. The validity of the proposed heuristic scheme is evaluated through experiments. Experimental results confirm the superiority of the heuristic scheme in terms of the energy saving improvement compared to the most related existing work.

Keywords: Schedule algorithm; Multi-core processor; Dynamic voltage scaling (DVS); Energy efficiency; Main memory (search for similar items in EconPapers)
Date: 2018
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Citations: View citations in EconPapers (1)

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DOI: 10.1007/s10878-017-0229-7

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