A neural network accelerated optimization method for FPGA

Zhengwei Hu (), Sijie Zhu (), Leilei Wang (), Wangbin Cao () and Zhiyuan Xie ()
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Zhengwei Hu: North China Electric Power University
Sijie Zhu: North China Electric Power University
Leilei Wang: North China Electric Power University
Wangbin Cao: North China Electric Power University
Zhiyuan Xie: North China Electric Power University

Journal of Combinatorial Optimization, 2024, vol. 47, issue 5, No 14, 28 pages

Abstract: Abstract A neural network accelerated optimization method for FPGA hardware platform is proposed. The method realizes the optimized deployment of neural network algorithms for FPGA hardware platforms from three aspects: computational speed, flexible transplantation, and development methods. Replacing multiplication based on Mitchell algorithm not only breaks through the speed bottleneck of neural network hardware acceleration caused by long multiplication period, but also makes the parallel acceleration of neural network algorithm get rid of the dependence on the number of hardware multipliers in FPGA, which can give full play to the advantages of FPGA parallel acceleration and maximize the computing speed. Based on the configurable strategy of neural network parameters, the number of network layers and nodes within layers can be adjusted according to different logical resource of FPGA, improving the flexibility of neural network transplantation. The adoption of HLS development method overcomes the shortcomings of RTL method in designing complex neural network algorithms, such as high difficulty in development and long development cycle. Using the Cyclone V SE 5CSEBA6U23I7 FPGA as the target device, a parameter configurable BP neural network was designed based on the proposed method. The usage of logical resources such as ALUT, Flip-Flop, RAM, and DSP were 39.6%, 40%, 56.9%, and 18.3% of the pre-optimized ones, respectively. The feasibility of the proposed method was verified using MNIST digital recognition and facial recognition as application scenarios. Compare to pre-optimization, the test time of MNIST number recognition is reduced to 67.58%, and the success rate was lost 0.195%. The test time for facial recognition applications was reduced to 69.571%, and the success rate of combining LDA algorithm was lost within 4%.

Keywords: Field programmable gate array; Neural network; Hardware acceleration; Mitchell algorithm; High-level synthesis (search for similar items in EconPapers)
Date: 2024
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DOI: 10.1007/s10878-024-01117-x

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