Hardware implementation of fault tolerance NoC core mapping

Naresh Kumar Reddy Beechu (), Vasantha Moodabettu Harishchandra and Nithin Kumar Yernad Balachandra
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Naresh Kumar Reddy Beechu: National Institute of Technology
Vasantha Moodabettu Harishchandra: National Institute of Technology
Nithin Kumar Yernad Balachandra: National Institute of Technology

Telecommunication Systems: Modelling, Analysis, Design and Management, 2018, vol. 68, issue 4, No 2, 630 pages

Abstract: Abstract Due to performance and reliability, network on chip (NoC) is considered to be the future generation interconnect technique for multiple cores in a chip. This paper proposes a system level core mapping technique which improves the performance of the whole system, while rectifying the temporary faults and permanent faults in the system using error correcting codes and spare core. This technique mainly focuses on the core mapping and faults on the system. This results in reliable core mapping and improved performance when a fault-related error occurs on an NoC. At last, the proposed core mapping technique is simulated and verified on FPGA board (Kintex-7 FPGA KC705 Evaluation Kit).

Keywords: System on chip (SoC); Network on chip (NoC); Core; Spare core placement; Kintex-7 FPGA KC705 Evaluation Kit (search for similar items in EconPapers)
Date: 2018
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DOI: 10.1007/s11235-017-0412-2

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