FPGA-based hardware accelerator for SIC in uplink NOMA networks

Sreenu Sunkaraboina () and Kalpana Naidu ()
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Sreenu Sunkaraboina: NIT Warangal
Kalpana Naidu: NIT Warangal

Telecommunication Systems: Modelling, Analysis, Design and Management, 2024, vol. 86, issue 2, No 10, 383-392

Abstract: Abstract Non-Orthogonal Multiple Access (NOMA) is an emerging multiple access scheme for the fifth-generation (5G) and beyond 5G mobile communications. Since NOMA supports a massive number of users simultaneously in a single time/frequency resource block through power domain multiplexing. However, the “Successive Interference Cancellation (SIC)” decoding technique at the receiver is an intricate task in the NOMA systems. Even though SIC operates in a sequential manner, multiple parallel SIC operations can be performed when deploying user pairing. Hence, outsourcing the efficient parallel processing devices is a suitable solution to compute all clusters SIC swiftly. In this paper, we design an efficient high-speed FPGA-based hardware accelerator for SIC implementation in uplink NOMA systems with user pairing on the 32-bit low-memory edge device (PYNQ-Z2 board). Ultimately, experimental results corroborate that the proposed accelerator design provides better SIC computation time than the NVIDIA Tesla K80 Graphics Processing Unit, Central Processing Unit, and ARM-Processor on PYNQ-Z2 board.

Keywords: 5G and beyond networks; Uplink NOMA; Successive interference cancellation; User pairing; PYNQ-Z2 (search for similar items in EconPapers)
Date: 2024
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DOI: 10.1007/s11235-024-01144-3

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