Integrating Operations Research into Very Large-Scale Integrated Circuits Placement Design: A Review

Binqi Zhang (), Lu Zhen, Shuaian Wang () and Fajun Yang ()
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Binqi Zhang: School of Management, Shanghai University, Shanghai, P. R. China
Lu Zhen: School of Management, Shanghai University, Shanghai, P. R. China
Shuaian Wang: Department of Logistics and Maritime Studies, The Hong Kong Polytechnic University, Kowloon, Hong Kong
Fajun Yang: School of Management, Shanghai University, Shanghai, P. R. China

Asia-Pacific Journal of Operational Research (APJOR), 2024, vol. 41, issue 06, 1-29

Abstract: The placement stage of the physical design of very large-scale integrated circuits (VLSI) specifies the arrangement and order of standard cells and devices within an area, and the effectiveness of the placement result directly affects the chip’s performance. The advancement of process standards and reduction in the size of features size have dramatically increased the complexity of placement design. The realization of placement algorithms to deal with millions of cells has thus become an important issue in the automation of integrated circuit electronic design. In this paper, we first segment the digital integrated circuits into VLSI design styles and review them from the perspectives of practical placement problems, placement design ideas, and placement optimization methods. The discussion around traditional circuits focuses on the essence of the placement problem, placement steps, and classification of placement algorithms. In modern circuit placement, the discussion focuses on the impact of technical constraints on design. After identifying the essence of the placement problem, solutions to the packing problem are reviewed, and we then summarize our representative placement algorithms. Finally, based on the development of VLSI placement design, the optimization bottlenecks of existing placement design are summarized, and suggestions for future research are made based on the latest research topics and methodologies.

Keywords: VLSI placement; placement design; mixed-cell-height; operational optimization (search for similar items in EconPapers)
Date: 2024
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DOI: 10.1142/S0217595924500076

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