An Accelerated Variable Stage Size Carry Skip Adder Realization Using 1S1R Resistive Memory

U. Dilna () and S. N. Prasad
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U. Dilna: School of Electronics and Communication Engineering, REVA University, Bangalore, Karnataka 560064, India
S. N. Prasad: School of Electronics and Communication Engineering, REVA University, Bangalore, Karnataka 560064, India†Department of Electrical and Electronics Engineering, Manipal Institute of Technology Bengaluru, Manipal Academy of Higher Education (MAHE), Manipal, Karnataka 576104, India

International Journal of Information Technology & Decision Making (IJITDM), 2024, vol. 23, issue 03, 1335-1365

Abstract: In-memory computing is the method of running computer computations completely in memory. Memristive device (e.g., 1 selector-1 resistor (1S1R)) is preferably utilized for in-memory computing with the appearance of hybrid CMOS nano-crossbar arrays. The parallelism of resistive arrays is considered in parallel adder designs to reduce the critical path delay. However, they minimize latency at the cost of hardware resources. In addition, the resistive random-access memory (ReRAM) is suffered by sneak–path problem because of the incapability for accessing a specific cell without impeding its neighbors. To tackle this issue, an analytical model of Pt/TaOx/TiO2/TaOx/Pt selector device is developed and it is integrated with ReRAM model for reducing the sneak path current. In this paper, a novel mapping scheme is proposed for in-memory variable stage size carry skip adder (VSS-CSKA) to harness the parallelism of 1S1R resistive memory. The VSS-CSKA considers variable block lengths and uses basic Boolean functions as skip logic to improve the speed without requiring huge area. Also, the selector device is modeled by considering the Pt/TaOx/TiO2/TaOx/Pt crested barrier for suppressing the sneak current in the resistive memory. The macro-model of the 1S1R resistive memory model is modeled in Verilog-A netlist and the simulations are executed on Spectre circuit simulator from Cadence Virtuoso. The proposed in-memory adder reduced the latency to 6 + 3log2(k) for k-bit addition and it consumes less energy because of the minimization of sneak currents in 1S1R.

Keywords: In-memory computing; one selector-one resistor (1S1R); variable stage size carry skip adder (VSS-CSKA); selector device and sneak currents (search for similar items in EconPapers)
Date: 2024
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DOI: 10.1142/S0219622023500414

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