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Fpga Synthesis And Validation Of Parallel Prefix Adders

Qasem Abu Al-Haija (), Mohamad Musab Asad, Ibrahim Marouf, Ahmad Bakhuraibah and Hesham Enshasy
Additional contact information
Qasem Abu Al-Haija: Department of Electrical Engineering, King Faisal University, Al-Ahsa, 31982, P.O. Box 380, SaudiArabia
Mohamad Musab Asad: University of Bristol, Department of Electrical & Electronic Engineering, Bristol, BS8 1QU, United Kingdom.
Ibrahim Marouf: Department of Electrical Engineering, King Faisal University, Al-Ahsa, 31982, P.O. Box 380, SaudiArabia
Ahmad Bakhuraibah: Department of Electrical Engineering, King Faisal University, Al-Ahsa, 31982, P.O. Box 380, Saudi Arabia
Hesham Enshasy: Department of Electrical Engineering, King Faisal University, Al-Ahsa, 31982, P.O. Box 380, Saudi Arabia

Acta Electronica Malaysia (AEM), 2019, vol. 3, issue 2, 31-36

Abstract: The main objective of this paper is to attain the best achievable time delay reduction with better performance (i.e. frequency) running on FPGA platforms and prove their applicability in high performance reconfigurable computing in addition to evaluate the FPGA design area and thermal power dispassion. The paper presents description on the implementation of five fast radix-2 parallel prefix adders, namely: Ladner-Fischer Adder (LFA), Brent-Kung Adder (BKA), Kogge-Stone Adder (KSA), Hans-Carlson Adder (HCA), and Sklansky Adder (SkA), with variable data path sizes ranging from 8 bits to 64 bits. The PPA topologies were implemented using VHDL description language and synthesized using Altera Cyclone IV E (EP4CE115 F29C7) FPGA chip device. Intensive tests and verifications were conducted and analyzed validate and evaluate the design cost factors: total path delay time, maximum frequency, design area and the total FPGA thermal power dissipations of the FPGA design as well as the hardware utilization. The results on the code synthesizing demonstrated that the proposed FPGA implementation of KSA has recorded the best values of critical path delay with 4.504 ns for 64 bits while BKA recorded the least design area results with 223 logic elements for the same bit length. In terms of power dissipation, KSA and SkA adders have recorded the best outcomes since they consume the minimum total thermal power dissipation among all other PPAs and for all bit lengths. Thus, the performance of the proposed PPA adders was benchmarked against other state-of-the-art designs which results reflected its superiority in terms of throughput of two or more multiple times as compared to others.

Keywords: FPGA Design; Parallel Prefix Adders (PPAs); Kogge-Stone Adder (KSA); Brent-Kung Adder (BKA); Han-Carlson Adder (HCA); Sklansky Adder (SkA); Ladner-Fischer Adder (LFA); Critical Path Delay; FPGA Synthsize Area; FPGA thermal power dissipation. (search for similar items in EconPapers)
Date: 2019
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Persistent link: https://EconPapers.repec.org/RePEc:zib:zbnaem:v:3:y:2019:i:2:p:31-36

DOI: 10.26480/aem.02.2019.31.36

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