Comparison Of Instruction Scheduling And Register Allocation For Mips And Hpl -Pd Architecture For Exploitation Of Instruction Level Parallelism

Rajendra Kumar ()
Additional contact information
Rajendra Kumar: Vidya College of Engineering, Meerut (India)

Engineering Heritage Journal (GWK), 2018, vol. 2, issue 2, 4-8

Abstract: The integrated approaches for instruction scheduling and register allocation have been promising area of research for code generation and compiler optimization. In this paper we have proposed an integrated algorithm for instruction scheduling and register allocation and implemented it for compiler optimization in machine description in trimaran infrastructure for exploitation of Instruction level parallelism. Our implementation in trimaran infrastructure shows that our scheduler reduces the number of active live ranges dealt with linear scan allocator. As a result only few spills were needed and the quality of the code generated was improved. For our experiments we used 20 benchmarks available with trimaran infrastructure for HPL-PD architecture. We compare some of these results with results obtained by Haijing Tang et al (2013) performed by LLVM compiler on MIPS architecture. For our experimental work we added machine description (MDES) targeted to HL-PD architecture. The implemented algorithm is based on subgraph isomorphism. The input program is represented in the form of directed acyclic graph (DAG). The vertices of the DAG represent the instructions, input and output operands of the program, while the edges represent dependencies among the instructions.

Keywords: ILP; Instruction Scheduling; Register Allocation; Trimaran Simulator; Parallelilsm. (search for similar items in EconPapers)
Date: 2018
References: View complete reference list from CitEc
Citations:

Downloads: (external link)
https://enggheritage.com/download/13764/ (application/pdf)

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:zib:zbngwk:v:2:y:2018:i:2:p:4-8

DOI: 10.26480/gwk.01.2018.04.08

Access Statistics for this article

Engineering Heritage Journal (GWK) is currently edited by Dr. Nastaein Qamaruz Zaman

More articles in Engineering Heritage Journal (GWK) from Zibeline International Publishing
Bibliographic data for series maintained by Zibeline International Publishing ( this e-mail address is bad, please contact ).