Performance Analysis of Shared-Memory Bus-Based Multiprocessors Using Timed Petri Nets

Wlodek Zuberek

A chapter in Petri Nets in Science and Engineering from IntechOpen

Abstract: In shared-memory bus-based multiprocessors, the number of processors is often limited by the (shared) bus; when the utilization of the bus approaches 100%, processors spend an increasing amount of time waiting to get access to the bus (and shared memory) and this degrades their performance. The limitations imposed by the bus depend upon many parameters, and different parameters affect the performance in different ways. This chapter uses timed Petri nets to model shared-memory bus-based multiprocessors at the instruction execution level and shows how the performance of processors and the system are affected by different modeling parameters. Discrete-event simulation of the developed net models is used to get performance results.

Keywords: shared-memory multiprocessors; bus-based multiprocessors; timed Petri nets; performance analysis; discrete-event simulation (search for similar items in EconPapers)
JEL-codes: C60 (search for similar items in EconPapers)
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Persistent link: https://EconPapers.repec.org/RePEc:ito:pchaps:144940

DOI: 10.5772/intechopen.75589

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