FPGA Implementation and Carrier Recovery Based on Costas Loop

Jing Zhang () and Ying Liu ()
Additional contact information
Jing Zhang: Beijing Jiaotong University
Ying Liu: Beijing Jiaotong University

A chapter in LISS 2023, 2024, pp 127-137 from Springer

Abstract: Abstract In order to solve the frequency offset caused by the inconsistence of RF transceiver frequency, the Costas loop algorithm is used to realize carrier synchronization. On the basis of analyzing the principle of the algorithm, the feasibility of Costas loop algorithm based on arctangent in the actual transceiver environment is verified by combining MATLAB with the actual transceiver environment. In FPGA based engineering implementation, table lookup method is used to reduce the time delay of feedback loop and thus reduce the clock frequency of FPGA. Simulation and engineering verification show that the loop implemented in this work can realize carrier synchronization, provide correct data for subsequent demodulation and decoding, and realize synchronous demodulation of BPSK modulated signals.

Keywords: Costas Loop; Carrier Synchronization; FPGA; BPSK; Reduce Time Delay (search for similar items in EconPapers)
Date: 2024
References: Add references at CitEc
Citations:

There are no downloads for this item, see the EconPapers FAQ for hints about obtaining it.

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:spr:lnopch:978-981-97-4045-1_11

Ordering information: This item can be ordered from
http://www.springer.com/9789819740451

DOI: 10.1007/978-981-97-4045-1_11

Access Statistics for this chapter

More chapters in Lecture Notes in Operations Research from Springer
Bibliographic data for series maintained by Sonal Shukla () and Springer Nature Abstracting and Indexing ().