Implementation of Scan Logic and Pattern Generation for RTL Design

R. Madhura and M. J. Shantiprasad
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R. Madhura: Dayananda Sagar College of Engineering, Department of Electronics and Communication
M. J. Shantiprasad: Cambridge Institute of Technology, Department of Electronics and Communication

A chapter in New Trends in Computational Vision and Bio-inspired Computing, 2020, pp 385-396 from Springer

Abstract: Abstract This paper presents test logic insertion and pattern generation for RTL designs. Test logic is the circuitry that the tool adds to improve the testability of design. Some of the memory elements in the design do not have controllability on clocks and resets. Our proposed work implements scan logic to have controllability and observability on each and every node of the design and adopted EDT technique to generate patterns with improved compression of scan test data and reduction in test time by controlling a large number of internal scan chains using small number of scan channels. Experimental results confirm that the proposed approach can significantly reduce test cost and test time with maximum possible fault and test coverage with ATPG effectiveness.

Keywords: DFT; Scan insertion; Compression; ATPG; RTL; EDT (search for similar items in EconPapers)
Date: 2020
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-030-41862-5_37

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DOI: 10.1007/978-3-030-41862-5_37

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