Machine Learning for Analog Circuit Sizing

Ahmet F. Budak (), Shuhan Zhang (), Mingjie Liu, Wei Shi, Keren Zhu and David Z. Pan
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Ahmet F. Budak: The University of Texas at Austin
Shuhan Zhang: The University of Texas at Austin
Mingjie Liu: The University of Texas at Austin
Wei Shi: The University of Texas at Austin
Keren Zhu: The University of Texas at Austin
David Z. Pan: The University of Texas at Austin

Chapter Chapter 12 in Machine Learning Applications in Electronic Design Automation, 2022, pp 307-335 from Springer

Abstract: Abstract Analog integrated circuit (IC) design is a labor-intensive process amid the lack of automation tools. Sizing of devices, as a key step in analog circuit synthesis, raises many research interests recently, because of both the industrial needs and the advance in machine learning (ML)-inspired algorithms. This chapter first introduces and formulates the analog circuit sizing problem. A brief overview on conventional analog circuit sizing algorithms is also presented. We then review and analyze several recently proposed methods on analog sizing, highlighting the adoption of ML techniques. Finally, we summarize the challenges and opportunities in applying ML for analog circuit sizing problem.

Keywords: Analog sizing; Machine learning; Bayesian optimization; Reinforcement learning; Parasitic prediction; Graph neural network (search for similar items in EconPapers)
Date: 2022
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-031-13074-8_12

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DOI: 10.1007/978-3-031-13074-8_12

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