Machine Learning for Analog Layout

Steven M. Burns, Hao Chen, Tonmoy Dhar, Ramesh Harjani, Jiang Hu, Nibedita Karmokar, Kishor Kunal, Yaguang Li, Yishuang Lin, Mingjie Liu, Meghna Madhusudan, Parijat Mukherjee, David Z. Pan (), Jitesh Poojary, S. Ramprasath, Sachin S. Sapatnekar (), Arvind K. Sharma, Wenbin Xu, Soner Yaldiz and Keren Zhu
Additional contact information
Steven M. Burns: Intel Labs
Hao Chen: Texas A&M University
Tonmoy Dhar: The University of Texas at Austin
Ramesh Harjani: The University of Texas at Austin
Jiang Hu: University of Minnesota
Nibedita Karmokar: The University of Texas at Austin
Kishor Kunal: The University of Texas at Austin
Yaguang Li: University of Minnesota
Yishuang Lin: University of Minnesota
Mingjie Liu: Texas A&M University
Meghna Madhusudan: The University of Texas at Austin
Parijat Mukherjee: Intel Labs
David Z. Pan: Texas A&M University
Jitesh Poojary: The University of Texas at Austin
S. Ramprasath: The University of Texas at Austin
Sachin S. Sapatnekar: The University of Texas at Austin
Arvind K. Sharma: The University of Texas at Austin
Wenbin Xu: University of Minnesota
Soner Yaldiz: Intel Labs
Keren Zhu: Texas A&M University

Chapter Chapter 17 in Machine Learning Applications in Electronic Design Automation, 2022, pp 505-544 from Springer

Abstract: Abstract The performance of analog circuits is critically dependent on layout parasitics, but layout has traditionally been a manual and time-consuming task. Recent advances in ML have enabled new capabilities to facilitate fast automated placement and routing. This chapter presents an overview of these techniques, including geometric constraint generation and constrained placement and routing. A variety of ML techniques are used in various steps of analog placement and routing, including graph neural networks, random forest methods, support vector machines, graph attention networks, generative adversarial networks, reinforcement learning, and variational autoencoders. This chapter shows how these general ML algorithms are specifically customized to the requirements of optimized analog layout.

Keywords: Analog layout; Symmetry; Annotation; Graph neural networks; Deep neural networks; Layout performance prediction; Analog routing (search for similar items in EconPapers)
Date: 2022
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-031-13074-8_17

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DOI: 10.1007/978-3-031-13074-8_17

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