Validation of Hardware Events for Successful Performance Pattern Identification in High Performance Computing

Thomas Röhl (), Jan Eitzinger, Georg Hager and Gerhard Wellein
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Thomas Röhl: University of Erlangen-Nuremberg, Erlangen Regional Computing Center (RRZE)
Jan Eitzinger: University of Erlangen-Nuremberg, Erlangen Regional Computing Center (RRZE)
Georg Hager: University of Erlangen-Nuremberg, Erlangen Regional Computing Center (RRZE)
Gerhard Wellein: University of Erlangen-Nuremberg, Erlangen Regional Computing Center (RRZE)

Chapter Chapter 2 in Tools for High Performance Computing 2015, 2016, pp 17-28 from Springer

Abstract: Abstract Hardware performance monitoring (HPM) is a crucial ingredient of performance analysis tools. While there are interfaces like LIKWID, PAPI or the kernel interface perf_event which provide HPM access with some additional features, many higher level tools combine event counts with results retrieved from other sources like function call traces to derive (semi-)automatic performance advice. However, although HPM is available for x86 systems since the early 90s, only a small subset of the HPM features is used in practice. Performance patterns provide a more comprehensive approach, enabling the identification of various performance-limiting effects. Patterns address issues like bandwidth saturation, load imbalance, non-local data access in ccNUMA systems, or false sharing of cache lines. This work defines HPM event sets that are best suited to identify a selection of performance patterns on the Intel Haswell processor. We validate the chosen event sets for accuracy in order to arrive at a reliable pattern detection mechanism and point out shortcomings that cannot be easily circumvented due to bugs or limitations in the hardware.

Keywords: Home Agent; Cache Line; Event Count; Performance Pattern; Load Imbalance (search for similar items in EconPapers)
Date: 2016
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DOI: 10.1007/978-3-319-39589-0_2

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