Power Management and Event Verification in PAPI

Heike Jagode (), Asim YarKhan, Anthony Danalis and Jack Dongarra
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Heike Jagode: University of Tennessee, Knoxville, Innovative Computing Laboratory
Asim YarKhan: University of Tennessee, Knoxville, Innovative Computing Laboratory
Anthony Danalis: University of Tennessee, Knoxville, Innovative Computing Laboratory
Jack Dongarra: University of Tennessee, Knoxville, Innovative Computing Laboratory

Chapter Chapter 4 in Tools for High Performance Computing 2015, 2016, pp 41-51 from Springer

Abstract: Abstract For more than a decade, the PAPI performance monitoring library has helped to implement the familiar maxim attributed to Lord Kelvin: “If you cannot measure it, you cannot improve it.” Widely deployed and widely used, PAPI provides a generic, portable interface for the hardware performance counters available on all modern CPUs and some other components of interest that are scattered across the chip and system. Recent and radical changes in processor and system design—systems that combine multicore CPUs and accelerators, shared and distributed memory, PCI-express and other interconnects—as well as the emergence of power efficiency as a primary design constraint, and reduced data movement as a primary programming goal, pose new challenges and bring new opportunities to PAPI. We discuss new developments of PAPI that allow for multiple sources of performance data to be measured simultaneously via a common software interface. Specifically, a new PAPI component that controls power is discussed. We explore the challenges of shared hardware counters that include system-wide measurements in existing multicore architectures. We conclude with an exploration of future directions for the PAPI interface.

Keywords: Hardware Performance Counters; Paper Components; Primary Program Goals; Running Average Power Limit (RAPL); Region-specific Models (MSRs) (search for similar items in EconPapers)
Date: 2016
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DOI: 10.1007/978-3-319-39589-0_4

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