Vectorization of High-Order DG in Ateles for the NEC SX-ACE

Harald Klimach (), Jiaxing Qi (), Stephan Walter () and Sabine Roller ()
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Harald Klimach: University of Siegen
Jiaxing Qi: University of Siegen
Stephan Walter: Höchstleistungsrechenzentrum Stuttgart
Sabine Roller: University of Siegen

A chapter in Sustained Simulation Performance 2017, 2017, pp 75-88 from Springer

Abstract: Abstract In this chapter, we investigate the possibilities of deploying a high-order, modal, discontinuous Galerkin scheme on the SX-ACE. Our implementation Ateles is written in modern Fortran and requires the new sxf03 compiler from NEC. It is based on an unstructured mesh representation that necessitates indirect addressing, but allows for a large flexibility in the representation of geometries. However, the degrees of freedom within the elements are stored in a rigid, structured array. For sufficiently high-order approximations these data structures within the elements can be exploited for vectorization.

Keywords: Discontinuous Galerkin Scheme; Ateles; Modern Fortran; FLOP Ratio; High Order Discontinuous Galerkin Schemes (search for similar items in EconPapers)
Date: 2017
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Persistent link: https://EconPapers.repec.org/RePEc:spr:sprchp:978-3-319-66896-3_5

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DOI: 10.1007/978-3-319-66896-3_5

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